/*
 * Copyright (c) 2012, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_ARMGLOBALTIMER_REGISTERS_H__
#define __HW_ARMGLOBALTIMER_REGISTERS_H__

#include "regs.h"

/*
 * i.MX6UL ARMGLOBALTIMER
 *
 * ARM Cortex-A9 Global Timer
 *
 * Registers defined in this header file:
 * - HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers
 * - HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
 * - HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register
 * - HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers
 * - HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register
 *
 * - hw_armglobaltimer_t - Struct containing all module registers.
 */

//! @name Module base addresses
//@{
#ifndef REGS_ARMGLOBALTIMER_BASE
#define HW_ARMGLOBALTIMER_INSTANCE_COUNT (1) //!< Number of instances of the ARMGLOBALTIMER module.
#define REGS_ARMGLOBALTIMER_BASE (0x021DC000) //!< Base address for ARMGLOBALTIMER.
#endif
//@}


//-------------------------------------------------------------------------------------------
// HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register (RW)
 *
 * Reset value: 0x00000000
 *
 * Configuration and control of the Global Timer.
 */
typedef union _hw_armglobaltimer_control
{
    reg32_t U;
    struct _hw_armglobaltimer_control_bitfields
    {
        unsigned TIMER_ENABLE : 1; //!< [0] Timer enable.
        unsigned DBG_ENABLE : 1; //!< [1] This bit is banked per Cortex-A9 processor.
        unsigned RESERVED0 : 6; //!< [2] This bit is banked per Cortex-A9 processor.
        unsigned FCR0 : 1; //!< [3] This bit is banked per Cortex-A9 processor.
        unsigned FCR1 : 1; //!< [7:4] Reserved
        unsigned RESERVED1 : 22; //!< [31:16] Reserved.
    } B;
} hw_armglobaltimer_control_t;
#endif

/*!
 * @name Constants and macros for entire ARMGLOBALTIMER_CONTROL register
 */
//@{
#define HW_ARMGLOBALTIMER_CONTROL_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x000)

#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_CONTROL           (*(volatile hw_armglobaltimer_control_t *) HW_ARMGLOBALTIMER_CONTROL_ADDR)
#define HW_ARMGLOBALTIMER_CONTROL_RD()      (HW_ARMGLOBALTIMER_CONTROL.U)
#define HW_ARMGLOBALTIMER_CONTROL_WR(v)     (HW_ARMGLOBALTIMER_CONTROL.U = (v))
#define HW_ARMGLOBALTIMER_CONTROL_SET(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() |  (v)))
#define HW_ARMGLOBALTIMER_CONTROL_CLR(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() & ~(v)))
#define HW_ARMGLOBALTIMER_CONTROL_TOG(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() ^  (v)))
#endif
//@}


#define HW_ARMGLOBALTIMER_COUNTER_LO_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x008)

#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_COUNTER_LO           (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_LO_ADDR)
#define HW_ARMGLOBALTIMER_COUNTER_LO_RD()      (HW_ARMGLOBALTIMER_COUNTER_LO)
#define HW_ARMGLOBALTIMER_COUNTER_LO_WR(v)     (HW_ARMGLOBALTIMER_COUNTER_LO = (v))
#endif

#define HW_ARMGLOBALTIMER_COUNTER_HI_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x00C)

#ifndef __LANGUAGE_ASM__
#define HW_ARMGLOBALTIMER_COUNTER_HI           (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_HI_ADDR)
#define HW_ARMGLOBALTIMER_COUNTER_HI_RD()      (HW_ARMGLOBALTIMER_COUNTER_HI)
#define HW_ARMGLOBALTIMER_COUNTER_HI_WR(v)     (HW_ARMGLOBALTIMER_COUNTER_HI = (v))
#endif

#endif // __HW_ARMGLOBALTIMER_REGISTERS_H__

